Method to efficiently reduce the number of connections in a...

Details Method to efficiently reduce the number of connections in a... Method to efficiently reduce the number of connections in a...

G - Physics

06

F

354/120, 354/230

G06F 15/00 (2006.01) G06F 17/50 (2006.01)

Patent

CA 1298666

YO9-86-103 A METHOD TO EFFICIENTLY REDUCE THE NUMBER OF CONNECTIONS IN A CLRCUIT Abstract A provided logic circuitry implementation in a given technology includes n signals and m nodes. A final logic circuitry implementation is produced therefrom which is the functional equivalent of, and contains fewer connections than, the provided logic circuitry implementation. A given one of the n signals is first processed, and global information is computed for this signal. A graphical representation of connections between the m nodes is derived from the computed global information. A list of nodes that form a cut set is produced from the graphical representation, and an optimized logic circuitry implementation is provided as a function thereof. Each of the remaining ones of the n signals are processed sequentially, as above, to form successive optimized logic circuitry implementations, with the processing of the nth signal resulting in the final logic circuitry implementation.

558107

Affiliated with

Also associated with

Rating

Method to efficiently reduce the number of connections in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to efficiently reduce the number of connections in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to efficiently reduce the number of connections in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1268121