G - Physics – 06 – F
Patent
G - Physics
06
F
328/129, 354/224
G06F 11/10 (2006.01)
Patent
CA 1283485
ABSTRACT OF THE DISCLOSURE MEMORY SYSTEM EMPLOYING A ZERO DC POWER GATE ARRAY FOR ERROR CORRECTION An error-correcting memory system includes a storage module which receives an address and which reads data bits and check bits at the address, and it further includes a zero DC power gate array which corrects errors in the data bits by decoding multiple minterms from the check bits wherein the gate array is comprised of a plurality of capacitors, one for each of the minterms; a control circuit for generating a control signal that is in one state when the minterms are to be detected and is otherwise in an opposite state; a charging circuit, coupled between the control circuit and the capacitors, for charging all of the capacitors only when the control signal is in its opposite state; and a discharging circuit, coupled between the control circuit and the capacitors, for indicating the presence of the minterms by selectively discharging the capacitors as a selectable decode of the check bits only when the control signal is in its one state.
530493
Chan Stephen Jab Chung
Peterson Luverne Ray
R. William Wray & Associates
Unisys Corporation
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