Floating point unit computation techniques

Details Floating point unit computation techniques Floating point unit computation techniques

G - Physics

06

F

354/197

G06F 7/50 (2006.01) G06F 5/01 (2006.01) G06F 7/52 (2006.01)

Patent

CA 1321650

ABSTRACT OF THE DISCLOSURE A system for use in a floating point computation unit for providing a sign/magniture subtraction operation, which system uses propagate/generate logic responsive to the subtraction operands to produce intermediate and final propagate and generate outputs. First carry computation logic is responsive to the final propagate and generate outputs and to a carry-in bit to produce final carry outputs and a carry-out bit. The latter outputs are used to produce a first subtraction result. Second carry computation logic responds to the intermediate propagate and generate outputs to produce second final carry outputs. The latter outputs and selected intermediate propagate outputs are used to produce a second subtraction result. The carry-out bit then selects one of the two subtraction results as the final subtraction result. The floating point unit further normalizes an exponent result in conjunction with a mantissa result which is formed as a plurality of data slices. The number of leading zeros in each data slice is determined and each number of leading zeros is subtracted from the exponent result to produce a plurality of subtracted results. One of the subtracted results is then selected as the normalized exponent result.

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