Photolithographic process for fabricating thin film transistors

Details Photolithographic process for fabricating thin film transistors Photolithographic process for fabricating thin film transistors

H - Electricity

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L

356/178

H01L 21/283 (2006.01) H01L 21/84 (2006.01) H01L 29/786 (2006.01)

Patent

CA 1202121

ABSTRACT A photolithographic method for fabricating thin film transistors and thin film transistor arrays in which the contamination vulnerable semi- conductor-insulator interfaces are formed in a single vacuum pump-down operation. To minimize step coverage problems, quasi-planar construction is employed to provide a planar substructure for receipt of the deposited thin semiconductor layer.

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