Ram memory overlay gate array circuit

Details Ram memory overlay gate array circuit Ram memory overlay gate array circuit

G - Physics

06

F

354/239

G06F 13/14 (2006.01) G06F 12/06 (2006.01)

Patent

CA 1273124

RAM MEMORY OVERLAY GATE ARRAY CIRCUIT ABSTRACT OF THE INVENTION This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocecsor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology,

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