Synchronous data receiver circuit

Details Synchronous data receiver circuit Synchronous data receiver circuit

H - Electricity

04

B

325/17, 325/72

H04B 1/40 (2006.01) H04L 7/04 (2006.01) H04L 7/10 (2006.01)

Patent

CA 1236167

ABSTRACT OF THE DISCLOSURE The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on. (FIG. 6)

484728

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