Memory test method and apparatus

Details Memory test method and apparatus Memory test method and apparatus

G - Physics

11

C

354/224

G11C 29/00 (2006.01) G11C 29/10 (2006.01) G11C 29/20 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1304164

ABSTRACT OF THE INVENTION A method and apparatus for memory testing is described. A first pattern of data is written into the memory in a pseudo-random address sequence determined by an address generator. The first pattern is read from the memory and checked for any error. A second pattern that is the complement of the first pattern is written into the memory in a pseudo- random address sequence determined by the address generator. The second pattern is read from the memory and checked for any errors. A third pattern of data is written into the memory in the pseudo-random address sequence determined by the address generator. The third pattern of data has the effect of complementing respective check bits which are the same for the first pattern of data and the second pattern of data. The third pattern is read from memory and checked for any error.

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