Memory arrangement with ordered writing particularly...

Details Memory arrangement with ordered writing particularly... Memory arrangement with ordered writing particularly...

G - Physics

01

S

354/237

G01S 7/06 (2006.01) G01S 7/22 (2006.01) G11C 7/00 (2006.01)

Patent

CA 1200916

-14- ABSTRACT: There is disclosed a memory arrangement par- ticularly intended for cooperation with a radar image dis- play unit. the arrangement comprises a so-called "main memory" which contains the data words which are arranged in accordance with a set of addresses. The arrangement includes an input circuit having an output connected to the data input of the main memory and also at least one input for receiving an input word intended to be written into the main memory at an input address. This arrange- ment is characterized in that memory locations are pro- vided which are determined by the same set of addresses and a write circuit in these locations to write therein a first word at the same address, or a data word is written into the main memory and for writing therein a second word under the control of a so-called updating signal in all the addresses of the said set. The arrangement is further characterized in that the input circuit comprises a control element to provide that during reading, at the output of the main memory of a data word accompanied by the second word, an invalidation data word is entered into the main memory at this address.

431565

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