Digital filter circuits

Details Digital filter circuits Digital filter circuits

G - Physics

06

F

354/204, 328/0.3

G06F 7/50 (2006.01) H03H 17/02 (2006.01)

Patent

CA 1177175

RCA 76,854 ABSTRACT OF THE DISCLOSURE A digital filter is provided which selectively employs straight binary arithmetic and offset two's complement arithmetic in an adder ladder to protect against signal overflows and underflows, as well as to minimize adder size. Signal overflows and underflows are prevented by performing subtraction and certain additions in offset two's complement notation, while adder sizes are minimized by performing certain other additions in binary notation. In an alternate embodiment, positively weighted values are combined by binary addition in a first adder ladder, and negatively weighted values are combined by binary addition in a second, parallel adder ladder. At the outputs of the two ladders, the two sums are converted to offset two's complement notation, and the negatively weighted sum is subtracted from the positively weighted sum.

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