Dynamic ram refresh circuit

Details Dynamic ram refresh circuit Dynamic ram refresh circuit

G - Physics

11

C

354/237

G11C 7/00 (2006.01)

Patent

CA 1186066

DYNAMIC RAM REFRESH CIRCUIT ABSTRACT OF THE DISCLOSURE The present circuit provides an economical way of refreshing dynamic RAM memory. This circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit inter- lock control for the access of the RAM memory on a shared basis with the refresh circuit.

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