Digital threshold detector with hysteresis

Details Digital threshold detector with hysteresis Digital threshold detector with hysteresis

H - Electricity

04

N

328/173

H04N 5/14 (2006.01) H03K 3/037 (2006.01) H04N 5/213 (2006.01)

Patent

CA 1257345

ABSTRACT OF THE DISCLOSURE As the 8-bit input signal applied to a threshold device reaches a first threshold level, the 1-bit output signal changes from a logical zero to a logical one. The 1-bit output signal is delayed by one system clock period and fed back. The delayed 1-bit output signal is combined (e.g., merged or added) with the 8-bit input signal, and the resulting signal is applied to the threshold device to provide a hysteresis feature. Once the delayed 1-bit output signal becomes a logical one, the input signal has to drop below a second, lower threshold level before the 1-bit output signal can revert back to a logical zero, whereby a margin of noise immunity is provided.

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