Frame synchronization detection system

Details Frame synchronization detection system Frame synchronization detection system

H - Electricity

04

L

363/17

H04L 7/08 (2006.01) H04J 3/06 (2006.01)

Patent

CA 1255403

Abstract of the Disclosure In a frame synchronization system for synchronizing a frame consisting of N sub-frames each consisting of M bits, a transmitting side includes a circuit for generating an N-bit cyclic code from a generating polynomial and sequentially and respectively inserting bits of the cyclic code in bit positions of the sub-frames, and a receiving side includes a divider for dividing a code polynomial having N-bit values of the data trains as coefficients by the generating polynomial to output the remainder, and a frame synchronization detector for sending a frame synchronization clock signal to the N-bit data train producing circuit when the remainder from the divider is zero.

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