High speed packet switching arrangement

Details High speed packet switching arrangement High speed packet switching arrangement

H - Electricity

04

L

344/29

H04L 12/56 (2006.01)

Patent

CA 1260123

ABSTRACT A circuit arrangement is provided for switching serial data packets through a network destined for one of a plurality of possible outgoing lines (104, 106, 108). Minimal delay is achieved by shifting the data through a shift register (120) having length equivalent to the destination address of the incoming serial data packet. The shift register addresses a memory (126) which in turn controls a switch network (138) so that the incoming packet is switched with minimal delay to an appropriate outbound line. By utilizing random access memory to translate from destination address to switch position, the system may be altered to correct for changes in the overall network caused by network failures or expansion network or to allow dynamic load balancing by directing data through the switch to a control computer (134) which in turn rewrites the memory.

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