Process for the parallel-series code conversion of a...

Details Process for the parallel-series code conversion of a... Process for the parallel-series code conversion of a...

H - Electricity

04

L

354/105

H04L 25/49 (2006.01) H04N 7/56 (2006.01)

Patent

CA 1241121

ABSTRACT OF THE DISCLOSURE PROCESS FOR THE PARALLEL-SERIES CODE CONVERSION OF A PARALLEL DIGITAL TRAIN AND A DEVICE FOR THE TRANSMISSION OF DIGITIZED VIDEO SIGNALS USING SUCH A PROCESS The process for the code conversion of eight parallel bits into words with nine series bits uses among the nine-bit words on the one hand those having five "1" and four "0" and which do not have five consecutive bits and whereof none starts or finishes with four identical bits, as well as their complements to 1, and on the other words having six "1" and three "0" with a maximum of transitions, as well as their complements to 1. Two complementary digital frame synchronization words are chosen from among the nine-bit words not retained for coding and which are not found in a random series of coded words. 13

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