Vertical interval data blanker

Details Vertical interval data blanker Vertical interval data blanker

H - Electricity

04

N

350/20

H04N 7/16 (2006.01)

Patent

CA 1208760

ABSTRACT OF THE DISCLOSURE A composite sync signal is applied to an integrating circuit connected across the input of a normally conducting transistor. The transistor is driven nonconductive by the serrated vertical sync pulse to develop the leading edge of a square wave timing pulse for initiating counting of horizontal lines in the vertical interval. As the integrating circuit discharges, the transistor is driven conductive again to define the trailing edge of the timing pulse for initiating blanking of data on selected horizontal lines in the vertical interval. Blanking of post equalizing pulses is avoided by having the trailing edge of the timing pulse occur after the post equalizing pulses.

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