Error disbursing format for digital information and method...

Details Error disbursing format for digital information and method... Error disbursing format for digital information and method...

G - Physics

06

F

354/113, 354/223

G06F 12/16 (2006.01) G06F 11/10 (2006.01) G11B 20/18 (2006.01) H03M 13/27 (2006.01)

Patent

CA 1297192

ABSTRACT OF THE DISCLOSURE Multiple stage interleaving through a memory matrix is utilized to separate adjacently disposed bits from bytes of digital information, in a reorganized bit stream. At least two stages of interleaving are required for the preferred embodiments of the invention which achieves a bit separation distance equal to the bit capacity of a plurality of either the matrix columns or rows, with that plurality being the number of adjacently disposed bits in each byte of digital information.

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