Microprocessor with selective cache memory

Details Microprocessor with selective cache memory Microprocessor with selective cache memory

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1289265

MICROPROCESSOR WITH SELECTIVE CACHE MEMORY Abstract A signal processing system is described which has a processor, a random access memory for storage of data, a read- only memory for storage of both coefficients and instructions, and a selective cache memory for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read- only memory for use later in the program. An address sequencer can be used as a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system.

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