Microcode control of a parallel architecture microprocessor

Details Microcode control of a parallel architecture microprocessor Microcode control of a parallel architecture microprocessor

G - Physics

06

F

354/230.7, 354/2

G06F 9/28 (2006.01) G06F 9/26 (2006.01)

Patent

CA 1223969

MICROCODE CONTROL OF A PARALLEL ARCHITECTURE MICROPROCESSOR Abstract A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which re- quires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro operations are executed in subsequent cycles as a required subpro- cessor becomes available. The entire microin- struction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microin- struction are executed. At that time, the next microinstruction is fetched into the latch.

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