Method of making a high performance small area, thin film...

Details Method of making a high performance small area, thin film... Method of making a high performance small area, thin film...

H - Electricity

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356/149

H01L 21/36 (2006.01) H01L 21/308 (2006.01) H01L 21/336 (2006.01) H01L 29/786 (2006.01)

Patent

CA 1228180

ABSTRACT A method of making a high performance, small area thin film transistor having a drain region, an insulating layer, and a source region forming a non-coplanar surface with respect to a substrate is disclosed. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. Thus decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting the capacitance between the gate electrode and the source region.

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