H - Electricity – 03 – D
Patent
H - Electricity
03
D
340/205
H03D 3/24 (2006.01) H03L 7/081 (2006.01) H03L 7/091 (2006.01) H04L 7/033 (2006.01) H04L 7/00 (2006.01)
Patent
CA 1288839
DIGITAL PHASE LOCKED LOOP CLOCK RECOVERY SCHEME Abstract A digital clock recovery scheme is disclosed. A reference clock, is used to provide a plurality of N signals with different clock phases. The incoming data stream is sampled and clocked with the reference clock to generate a plurality of M samples for each data bit. The logic values of the M samples are then analyzed to determine the relationship between the current clock phase and the data bit transition. In particular, if all samples agree, the clock phase is correctly aligned with the data. If the clock phase is either leading or lagging the data,various samples will disagree. In the latter situation, the clock phase is adjusted until all samples agree, the particular clock which provides this state thus being defined as the recovered clock signal.
583286
Bergmann Ernest Eisenhardt
Staves Sherre Marie
American Telephone And Telegraph Company
Kirby Eades Gale Baker
LandOfFree
Digital phase locked loop clock recovery scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital phase locked loop clock recovery scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase locked loop clock recovery scheme will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1300632