G - Physics – 06 – F
Patent
G - Physics
06
F
354/197
G06F 7/50 (2006.01)
Patent
CA 1270955
A B S T R A C T For successively adding a series of floating point numbers, a floating point adder stage (Fig. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of inter- mediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (Fig. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (Fig. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occur- ring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage. GE9-86-007
550740
Bleher J. Hartmut
Gerlicher Axel T.
Rump Siegfried M.
Unkauf Dieter K.
International Business Machines Corporation
Saunders Raymond H.
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