Memory access control system

Details Memory access control system Memory access control system

G - Physics

06

F

354/241

G06F 12/08 (2006.01)

Patent

CA 1313423

Abstract of the Disclosure A memory access control system includes an address array having a bit representing validity of a content Of a cache memory and a bit representing a coincidence between a content of the cache memory and a content of main memory unit, a hit/miss judgement circuit for judging a hit/miss of the cache memory in accordance with an output from the address array, a replace level determination circuit for determining a replace level of the cache. memory when a cache miss occurs, a replace judgement circuit for detecting validity of block data of the replace level and a noncoincidence between the contents of the cache memory and the main memory unit in accordance with an address array output corresponding to the replace level r and for judging necessity for writing the block data Of the cache memory into the main memory unit, and an MMU controller for processing write and read operations of the main memory unit by one request when the necessity for writing the block data of the cache memory into the main memory unit occurs.

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