Memory controller with interleaved queuing apparatus

Details Memory controller with interleaved queuing apparatus Memory controller with interleaved queuing apparatus

G - Physics

06

F

354/237

G06F 13/28 (2006.01) G06F 13/16 (2006.01)

Patent

CA 1172771

ABSTRACT OF THE DISCLOSURE A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which elimi- nates processing delays particularly in cases where such requests involve multiword transfers over successive memo- ry cycles of operation.

389098

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