Fabrication process- for a dielectric isolated complementary ic

Details Fabrication process- for a dielectric isolated complementary ic Fabrication process- for a dielectric isolated complementary ic

H - Electricity

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H01L 21/76 (2006.01) H01L 21/74 (2006.01) H01L 21/762 (2006.01) H01L 21/8222 (2006.01)

Patent

CA 1219379

25307-122 ABSTRACT OF THE DISCLOSURE An improved method for fabricating an isolated region for dielectric isolated complementary IC is disclosed. In order to avoid the difficulty of mask alignment and patterning on a deep etched uneven surface of the substrate, the present inven- tion intends to align the pattern before etching. The etching to form the p-type and n-type islands on the surface of the substrate is done at the same time. Next on the surface of the substrate is grown a polysilicon layer. Then the substrate is lapped off from its back surface and removed, leaving the island parts in the polysilicon layer, which becomes a new substrate. FP-56045/T53

465141

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