Speed enhancement technique for cmos circuits

Details Speed enhancement technique for cmos circuits Speed enhancement technique for cmos circuits

H - Electricity

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H03K 19/017 (2006.01) G11C 8/06 (2006.01) G11C 8/18 (2006.01) H03K 5/15 (2006.01) H03K 5/1534 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1320544

8332-179 SPEED ENHANCEMENT TECHNIQUE FOR CMOS CIRCUITS ABSTRACT OF THE DISCLOSURE A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits. RCC029:ms

603717

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