Bus adapter unit for digital data processing system

G - Physics – 06 – F

Patent

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354/233

G06F 13/38 (2006.01) G06F 13/40 (2006.01)

Patent

CA 1303229

83-467 ABSTRACT OF THE DISCLOSURE A digital data processing system includes a plurality of processing subsystems, each including an adapter for enabling transfers between the resident subsystem and other subsystems. The adapter includes a master section which enables transfers of data initiated by the subsystem between the input/output bus and the higher level communications mechanism, a slave section which enables transfers of data between the higher level communications mechanism and the input/output bus initiated by another subsystem and an interprocessor communications mechanism for enabling the subsystem and other subsystems to communicate to thereby enable the other subsystems to perform control operations in connection with the subsystem.

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