Bus for data processing system with fault cycle operation

Details Bus for data processing system with fault cycle operation Bus for data processing system with fault cycle operation

G - Physics

06

F

354/225

G06F 11/28 (2006.01) G06F 11/07 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1209708

ABSTRACT OF THE DISCLOSURE A digital data processing system including a number of input/output units that communicate with a memory over an input/- output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/- output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/- output unit that initiated the transfer unit to enable it to recover.

445834

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