Full adder circuit

Details Full adder circuit Full adder circuit

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1232073

-16- ABSTRACT : "Full adder circuit". So as to generate quickly the several carry signals in a full adder circuit (for example a 40-bit circuit), tile circuit is divided into a plurality of sub-circuits of a first type, in which provisional carry signals are generated in parallel. Carry look-ahead circuits are of a dual construction, each first carry look-ahead circuit receiving a logic "O" and each second carry look-ahead circuit receiving a logic "1". So the provisional carry signals generated are complementary, from which the carry signal proper is selected with the aid of a multiplex switch. The multiplex switch is con- trolled by the carry signal generated in a preceding sub- circuit of the first type. Since a multiplex switch operates faster than 3-bit or 4-bit wide carry look-ahead circuits, which operate in parallel in groups, the carry signals are consequently generated faster.

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