Semiconductor memory

G - Physics – 11 – C

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G11C 7/00 (2006.01) G11C 5/02 (2006.01) G11C 7/10 (2006.01) G11C 8/00 (2006.01) G11C 8/14 (2006.01) G11C 11/34 (2006.01)

Patent

CA 1232354

ABSTRACT SEMICONDUCTOR MEMORY A novel memory structure for very big memory arrays on a chip is described whose memory array is divided in- to a number of subarrays (SA 1 to SA N). The subarrays are controlled via common word decoders and subarray decoders (WD and DSA, respectively). The word lines of the individual subarrays are individually selectable through word line switches (WS), and the bit lines of the subarrays are applied directly to a common line system (RB and WB), and interconnected in such a manner that the peripheral circuits as e.g. the data input and output circuits (DI and DO) can be arranged in practi- cally any free location on the chip.

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