Sequential data block address processing circuits

Details Sequential data block address processing circuits Sequential data block address processing circuits

G - Physics

06

F

352/18

G06F 11/00 (2006.01) G11B 20/10 (2006.01) G11B 20/18 (2006.01) G11B 27/10 (2006.01) G11B 27/36 (2006.01) H04N 5/782 (2006.01) H04N 5/935 (2006.01)

Patent

CA 1208775

ABSTRACT OF THE DISCLOSURE A sequential data block address processing circuit for deriving address signals in dependence on incoming data representing, for example, a digital television signal and formed by sequential blocks of data each including a block address which changes cyclically from block to block and which is formed of three address words respectively representing block, line and segment numbers which change cyclically, the circuit comprising a read-only memory operative for each incoming block address to increment the block number and if this incrementing involves a carry to increment the line number and so on up to the segment number, and further operative for each incoming block address to form a predicted next block address which is formed of three address words each representing the respective block, line or segment number or incremented number as appropriate, and a comparator to compare each predicted next block address with the next incoming block address and to supply a correct address indication only if there is identity between one or more of the compared block addresses, and an address regenerator which is locked to the block addresses in the incoming data if, and only if, the comparator is indicating identity between one or more of the compared block addresses.

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