Method for manufacturing vlsi complementary mos field effect...

Details Method for manufacturing vlsi complementary mos field effect... Method for manufacturing vlsi complementary mos field effect...

H - Electricity

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356/126, 356/149

H01L 21/82 (2006.01) H01L 21/8238 (2006.01) H01L 29/49 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1214885

ABSTRACT OF THE DISCLOSURE A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses dGOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness dGOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3 x 1011 cm-2 and an energy of 25 keV. In addition to achieving a high dielectric strength for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.

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