Bit generator having predetermined occurrence rate with...

Details Bit generator having predetermined occurrence rate with... Bit generator having predetermined occurrence rate with...

H - Electricity

03

K

328/97

H03K 3/84 (2006.01)

Patent

CA 1199687

Abstract of disclosure The electronic bit generator is comprised of a time base, a pseudorandom sequence generator, a counter (7) having the same capa- city as the pseudo-random sequence generator (12,15) and a comparator (10,8) of which one input is connected from the output (M1,Mn) of the pseudo-random sequence generator (12,15), and of which the other input is connected from the data output of the counter (7). The output of the comparator (10,8) is connected, on the one hand, to the reset input of, the counter (7) and, on the other hand, to the clock input of the pseduo-random sequence generator (12,15). The clock input of the counter (7) is connected from the output of the time base and the comparator output constitutes the output of the electro- nic bit generator. In the described embodiment, the comparator is comprised of stages (10.1 to 10.n) of which the number is equal to the length of the output binary word of the pseudo-random sequence generator (12, 15). Each stage (10.k) includes an exclusive-OR gate (n.k), the two inputs of which (P2k and P1k) are respectively connected from the outputs of the stages (7.k and 12.k) having the same rank in the pseudo-random sequence generator and in the counter. The output of the exclusive-OR gate (n.k) is connected to one input of a NAND gate (13.k) of which the other input is connected to a voltage source through a contact of a controllable switch (J.k), and of which the output is connected to the input of a AND gate (8) which is common to all the stages of the comparator, the output of the AND gate (8) being the electronic bit generator output.

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