Process for making complementary transistors

Details Process for making complementary transistors Process for making complementary transistors

H - Electricity

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H01L 21/02 (2006.01) H01L 21/762 (2006.01) H01L 21/8238 (2006.01)

Patent

CA 1191973

ABS Process for Making Complementary Transistors A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

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