G - Physics – 09 – G
Patent
G - Physics
09
G
375/4
G09G 1/16 (2006.01) G09G 5/34 (2006.01)
Patent
CA 1255404
-1- Video Display Control Circuit Arrangement Abstract of the Disclosure The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. During the alternate cycles (between refresh cycles) there may be a burst of signals from the signal path circuitry chip to write information into the bit map memory at some new address to effect scrolling. Instead of performing scrolling in the alternate cycles, information may be erased from a region. In the alternative there may be a burst of signals from an information source transmitted to the bit map memory to effect updating (i.e. writing new data information into the memory). The foregoing arrangement permits the entire bit map memory to be rewritten during the period required for one vertical scan of the video display device, which in turn enables the system to provide rapid smooth scrolling and continued sequential addressing of the memory.
511709
Forrester Ned C.
Furlong Thomas C.
Rose Robert C.
Digital Equipment Corporation
Moffat & Co.
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