G - Physics – 06 – F
Patent
G - Physics
06
F
354/239
G06F 9/455 (2006.01) G06F 9/445 (2006.01)
Patent
CA 1251284
UK9-85-006 ABSTRACT A microprocessor that has two operating modes for generating memory location addresses includes a processor 20 connected to a read-only memory 21, a random access memory 22 and an I/O unit 23 through control 25, data 26 and address 27 buses. A remapper unit 24 is connected between the processor 20 and the address bus so that when it is enabled by a signal from the I/O unit it can selectively change addresses generated by the processor and thus redirect the control of the microprocessor.
502056
International Business Machines Corporation
Saunders Raymond H.
LandOfFree
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