G - Physics – 06 – F
Patent
G - Physics
06
F
354/237
G06F 12/02 (2006.01) G06F 12/06 (2006.01)
Patent
CA 1304522
ABSTRACT Address generating apparatus for use in a computer system which includes a bus processor , a memory requiring 24-bit addresses, and a plurality of I/O processors, some of which generate 22-bit addresses and others of which generate 24-bit addresses on a system bus connecting them with the memory. The apparatus provides a 2-bit prefix to the address on the system bus when the address on the bus comes from a 22-bit device. The 22-bit devices are specified by a mask register and the prefixes by a set of prefix registers , one for each of the devices. When bus grant logic in the computer system determines which of the devices is to have control of the system bus, logic in the address generating apparatus determines from the mask register whether the device which is to receive control requires a prefix. If it does, the address generating apparatus outputs the device's prefix to the system bus's two most significant address lines at the same time as the device outputs a 22-bit address to the remaining address lines. The mask register and the prefix register are loadable from the bus processor by means of a bus which is independent of the system bus. On system initialization, the bus processor loads the mask register as required for the I/O devices on the system. During system operation, the bus processor loads prefixes for 22-bit devices as required for the devices to generate addresses for the area of memory from or to which the device is transferring data.
573274
Cheung Kin-Ling
Einarson Jeffrey W.
Samsung Electronics Co. Ltd.
Smart & Biggar
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