Vector data bypass mechanism for vector computer

Details Vector data bypass mechanism for vector computer Vector data bypass mechanism for vector computer

G - Physics

06

F

G06F 15/16 (2006.01) G06F 9/38 (2006.01) G06F 15/78 (2006.01) G06F 17/30 (2006.01)

Patent

CA 2157435

A bypass mechanism in a vector computer is disclosed. The vector register bypasses data to be written in the inner registers from input or output of the write data register. The bypass mechanism is mainly realized by a selector and a decoder. The selector selects any one of data to be written in the registers at the timing before 2 cycles, data to be written in the registers at the timing before 1 cycle, and the read data from the registers. The decoder controls the selector according to a mask signal from the mask register; a signal of a timing which is before one cycle of the mask signal, and a bypass signal from said controller.

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