Method and system for resetting fault tolerant computer system

Details Method and system for resetting fault tolerant computer system Method and system for resetting fault tolerant computer system

G - Physics

06

F

G06F 1/24 (2006.01) G06F 11/16 (2006.01)

Patent

CA 2530555

There is disclosed a method capable of resetting a fault tolerant computer in complete synchronization among modules. The method includes a step of generating a reset requesting signal by one of the modules, a step of dividing the reset requesting signal to first and second reset requesting signals, a step of transmitting the second reset requesting signal to the other module, a step of delaying the first reset requesting signal in the one module by a time required for transmitting the second reset requesting signal to the other module, a step of resetting at least one CPU included in the one module by a first CPU reset signal generated based on the first reset requesting signal delayed in the one module, and a step of resetting at least one CPU included in the other module by a second CPU reset signal generated based on the second reset requesting signal transmitted to the other module.

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