Frequency synthesizer using phase-locked loop

H - Electricity – 03 – L

Patent

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Details

H03L 7/18 (2006.01) H03J 7/06 (2006.01) H03L 7/087 (2006.01) H03L 7/183 (2006.01)

Patent

CA 2093040

In a phase locked loop frequency synthesizer having multiple feedback loops, a reference phase signal is developed into two signals having a frequency twice as high as the reference frequency and the phase difference of the two signals is a half wavelength. The output frequency produced by a voltage-controlled oscillator is divided by two frequency dividers in accordance with predetermined frequency division factors. Each of the frequency-divided signals and each of the developed signals are subjected to phase comparison in pairs. A voltage signal corresponding to the phase differences is fed through a low-pass filter and supplied to the voltage-controlled oscillator.

Dans un synthétiseur de fréquence à boucle à asservissement de phase comportant de multiples boucles de rétroaction, un signal de référence de phase est créé sous la forme de deux signaux ayant une fréquence double de celle de la fréquence de référence, la différence de phase entre ces deux signaux étant d'une demi-longueur d'onde. La fréquence de sortie d'un oscillateur commandé par la tension est divisée par deux diviseurs de fréquence selon des facteurs de division de fréquence prédéterminé. Chacun des signaux à fréquence divisée et chacun des signaux produits sont soumis à une comparaison de phase en paires. Un signal de tension correspondant à la différence de phase est appliqué à l'oscillateur commandé par la tension par l'intermédiaire d'un filtre passe-bas.

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