Mesh interconnected array in a fault-tolerant computer system

Details Mesh interconnected array in a fault-tolerant computer system Mesh interconnected array in a fault-tolerant computer system

G - Physics

06

F

G06F 15/163 (2006.01) G06F 11/00 (2006.01) G06F 11/18 (2006.01)

Patent

CA 2206840

This invention relates to fault-tolerant computer systems. Bus interface units (BIUs) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs) and memory or input/output (I/O) in a mesh interconnected array of a computer system. Errors are detected by self- checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. If self implicating errors are detected, the corresponding BIU is shut down, BIU configuration vectors are asserted onto the mesh and a consensus configuration vector is generated. If synchronization or memory bus errors are detected, corresponding error messages are asserted on the mesh and a reconfiguration algorithm is performed in order to generate a consensus configuration vector. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguration is minimized.

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