Multi-channel sonet/sdh desynchronizer

H - Electricity – 04 – L

Patent

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Details

H04L 29/02 (2006.01) H03L 7/081 (2006.01) H04J 3/07 (2006.01) H04L 7/00 (2006.01)

Patent

CA 2307044

A desynchronizer for desynchronizing one or multiple channels of SONET/SDH data signals, which includes a first in first out (FIFO) buffer having an input coupled to said data signals and an output for outputting asynchronous data obtained from one or more of said SONET/SDH data channels. An arithmetic unit coupled to the FIFO performs all operations required for single or multi-channel desynchronization. An endless phase modulator is coupled to the arithmetic unit and to the FIFO and is operative, in response to input from the arithmetic unit, to produce a single output desynchronized clock or multiple output desynchronized clocks.

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