One cycle register mapping

Details One cycle register mapping One cycle register mapping

G - Physics

06

F

G06F 12/02 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2042767

ABSTRACT A register map having a free list of available physcial locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physcial homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back up point during a trap event.

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