Method and apparatus for performing chip level equalization...

H - Electricity – 04 – B

Patent

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H04B 7/216 (2006.01)

Patent

CA 2591676

A method and apparatus for performing chip level equalization (CLE) using joint processing to enhance performance and system throughput using a transmitter having a plurality of transmit antennas and a receiver having a plurality of receive antennas. A channel response matrix is formed between the transmit antennas and the receive antennas to generate a joint channel correlation matrix between the transmit antennas and the receive antennas using a block-FFT (B-FFT) decomposition of the channel response matrix. Estimates of transmitted chip sequences from each of the transmit antennas are generated using minimum mean square error (MMSE) and the joint channel correlation matrix are combined. The combined estimate of the transmitted chip sequences are despread to recover transmitted data.

Procédé et appareil destinés à effectuer une égalisation du niveau de puce (CLE) au moyen d'un traitement conjoint pour améliorer les performances et le rendement du système grâce à un émetteur muni de plusieurs antennes émettrices et à un récepteur muni de plusieurs antennes réceptrices. Une matrice de réponse de canal est formée entre les antennes émettrices et les antennes réceptrices de manière à générer une matrice de corrélation de canal conjoint entre les antennes émettrices et les antennes réceptrices au moyen d'une décomposition de bloc-FFT (B-FFT) de la matrice de réponse de canal. Les estimations des séquences de puce émises par chacune des antennes émettrices sont générées au moyen de l'écart quadratique moyen minimal (MMSE) et corrélées avec la matrice de corrélation de canal conjointe. Les estimations combinées des séquences de puce émises sont désétalées de manière à récupérer les données émises.

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