Pipelined floating-point load instruction for microprocessor

Details Pipelined floating-point load instruction for microprocessor Pipelined floating-point load instruction for microprocessor

G - Physics

06

F

354/230.87

G06F 9/38 (2006.01) G06F 9/312 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2009744

A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.

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