Integrated circuit chip package and encapsulation process

H - Electricity – 01 – L

Patent

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Details

H01L 23/29 (2006.01) B29C 45/02 (2006.01) B29C 45/26 (2006.01) H01L 21/56 (2006.01) H01L 23/02 (2006.01) H01L 23/12 (2006.01) H01L 23/24 (2006.01) H01L 23/50 (2006.01)

Patent

CA 2180807

A method and resulting integrated circuit package is disclosed for encapsulatingintegrated circuit chips using transfer molding techniques in a form known as cavity packages. Each chip is positioned within a cavity surrounded by a laminate or printed wiring board which provides an array of contacts. The contacts provide for connections to an external circuit card and the contacts are also indirectly connected internally to the chip. The cavity, chip and some of the laminate, contacts and interconnections are on the same side of the carrier.Liquid plastic is forced into the cavity via a runner in a mold through a gate in the bottom of the carrier in order to encapsulate all of these components.

Cette invention concerne une méthode d'assemblage de circuits intégrés sous boîtier par encapsulation de puces selon des techniques de moulage par transfert en cavité. Chaque puce est positionnée dans une cavité entourée d'un stratifié ou d'une carte à circuits imprimés qui comporte une matrice de broches de contact. Ces broches servent à se raccorder à une carte à circuits externe et elles sont également raccordées indirectement à l'intérieur de la puce. La cavité, la puce et certaines connexions et interconnexions du stratifié se trouvent du même côté du substrat. Du plastique liquide est injecté dans la cavité via un canal de coulée du moule et une attaque de coulée au fond du substrat pour encapsuler tous ces composants.

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