Self-timed pipelined datapath system and asynchronous signal...

Details Self-timed pipelined datapath system and asynchronous signal... Self-timed pipelined datapath system and asynchronous signal...

G - Physics

06

F

G06F 13/14 (2006.01) G06F 1/32 (2006.01) G06F 9/38 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2230694

A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprising: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal. The state change of an active state to an inactive state of the combinational circuit is performed in consideration of the signal propagation time therein, whereby the issue of the request signal with respect to the combinational circuit at the preceding stage is delayed from the time the request signal with respect to the current combinational circuit is issued.

Système pipeline de données autosynchronisé. Le système réduit sa dissipation d'énergie en réglant exactement les états actifs et inactifs du circuit multi-seuils CMOS (MT-CMOS) qui lui sert de circuit combinatoire. Le circuit MT-CMOS comprend un circuit logique à seuil bas et un circuit de commande d'alimentation formé de transistors à seuil haut pour commander l'alimentation du circuit logique. Le système à pipeline de données autosynchronisé comprend : un circuit de pipeline de données comprenant un certain nombre d'étages de traitement de données ayant chacun un circuit combinatoire pour le traitement de données d'entrée et un registre connecté au côté entrée du circuit combinatoire; et un circuit de commande de signal asynchrone pour commander la transmission de données à destination et en provenance de chacun des registres du circuit de pipeline de données en réponse à un signal de demande. Le circuit combinatoire passe d'un état actif à un état inactif en fonction du temps pris par le signal pour s'y propager. Ainsi, l'émission du signal de demande relativement au circuit combinatoire à l'étage précédent est retardée par rapport au moment de l'émission du signal de demande relativement au circuit combinatoire de référence.

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