Stm mapping circuit and method

Details Stm mapping circuit and method Stm mapping circuit and method

H - Electricity

04

L

H04L 12/56 (2006.01) H04L 12/24 (2006.01)

Patent

CA 2377452

An STM mapping circuit is disclosed having a configuration that includes: a packet length detection circuit for generating byte effectiveness information that indicates whether byte data are effective data or not; routing circuits for generating routing information for rearranging byte data in a prescribed order while using byte effectiveness information to eliminate pad bytes; packet filter circuits for taking in packet data for each logical channel in accordance with channel number signals that indicate which logical channel the packet data belong to; M X M switches for sorting packet data for logical channel in a prescribed order while removing pad bytes in accordance with routing information; and packet memories that hold, for each logical channel, packet data that have been sorted by the M X M switches.

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