Method and circuit for improving the pointer processing in...

Details Method and circuit for improving the pointer processing in... Method and circuit for improving the pointer processing in...

H - Electricity

04

L

H04L 12/24 (2006.01) H04J 3/06 (2006.01)

Patent

CA 2287610

A method and circuit are described for improving the pointer processing in the case of synchronous digital hierarchy (SDH) transmission frames with VC4_4c, VC4_16c and VC4_64c concatenated payloads. The technique, proposed by the existing Standards, provides for two different state diagrams to be used in the pointer processing algorithm in case of concatenated or in case of non-concatenated payload, but no solution is disclosed for automatically going from the states of one diagram to the other. The present invention provides a circuit so constructed that it can be used in apparatus processing STM-4, STM-16 and STM-64 frames, through which the automatic recognition of the VC4-4c, VC4-16c and VC4-64c payload concatenation can be achieved. Therefore, it is not necessary to configure in advance the concatenation or non-concatenation condition.

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