System and method for instruction latency reduction in...

Details System and method for instruction latency reduction in... System and method for instruction latency reduction in...

G - Physics

06

F

G06F 9/45 (2006.01)

Patent

CA 2713649

A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.

L'invention concerne un système, un procédé et un appareil, dans lesquels un programmateur d'instruction d'un compilateur, par exemple un compilateur de nuanceur, réduit le temps de latence d'instruction sur la base d'une distance d'instruction déterminée entre un prédécesseur dépendant et des instructions de successeur.

Affiliated with

Also associated with

Rating

System and method for instruction latency reduction in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for instruction latency reduction in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for instruction latency reduction in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1480898