Stacked chip electronic package having laminate carrier and...

Details Stacked chip electronic package having laminate carrier and... Stacked chip electronic package having laminate carrier and...

H - Electricity

01

L

H01L 23/48 (2006.01) H01L 23/29 (2006.01) H01L 23/36 (2006.01) H01L 23/488 (2006.01) H01L 23/538 (2006.01) H01L 25/00 (2006.01) H01L 25/065 (2006.01) H01L 25/18 (2006.01) H05K 1/02 (2006.01) H05K 3/46 (2006.01) H01L 23/31 (2006.01) H05K 1/11 (2006.01)

Patent

CA 2455024

A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

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